The present invention relates to a semiconductor power component and a corresponding method of manufacture.
Although it is applicable to other similar semiconductor power components, the present invention as well as the problem underlying it are discussed with reference to a vertical IGBT (Insulated Gate Bipolar Transistor).
In general, IGBTs may be used as power switches in the range of some hundreds to some thousands of volts of blocking voltage. In particular, the use of IGBTs of this type as ignition transistors, i.e., as switches on the primary side of an ignition coil, may be of particular interest.
The structure of a vertical IGBT may be similar to that of a VDMOS transistor, although with the difference that, in the VDMOS transistor, on its anode side a p+-emitter may be arranged in place of an n+-substrate. German Published Patent Application No. 31 10 230 describes a vertical MOSFET component having the basic structure of a vertical IGBT.
In principle, two types of vertical IGBT, or V-IGBT may be distinguished in this context, namely the so-called punch-through IGBT (PT) and the so-called non-punch-through IGBT, as described, for example, in Laska et al., Solid State Electronics, Vol. 35, No. 5, pp. 681-685.
On the basis of FIGS. 7 and 8, the fundamental characteristics of these two IGBT types are described below.
FIG. 7 shows a schematic cross-sectional representation of an NPT-IGBT, whose active region, designated by reference numeral 200, has cell-shaped or strip-shaped MOS miniature-circuit-breaker assemblies 203, 206, 207, 208, 209. In this context, reference numeral 208 specifically designates a p-body zone, 206 an n+-source region, 207 a p+-contact region for joining p-body zone 208 to a cathode terminal 201, which at the same time is connected to n+-source region 206, 203 a gate terminal, 209 a gate oxide, and 210 an intermediate oxide. Furthermore, 204 designates an nxe2x88x92-drift region, 205 a reverse-side p+-emitter, and 202 an anode terminal.
The NPT-IGBT in accordance with FIG. 7 may be manufactured on a low-doped nxe2x88x92-substrate having a high charge carrier service life. After introducing the diffusion profile on front side VS of the wafer for producing MOS miniature-circuit-breaker assemblies 203, 206, 207, 208, 209, on rear side RS of the wafer, p+-emitter 205 is produced in very planar form having only a few xcexcm of penetration depth (d≈a few xcexcm) and having poor emitter efficiency. This transparent emitter region 205 functions to rapidly switch off the current in the dynamic operation of this component in order to assure that the shut-off losses are kept small. To achieve satisfactory forward properties despite such a poor emitter region 205, the carrier service life may need to be selected so as to be as high as possible in nxe2x88x92-drift region 204. In addition, the thickness of nxe2x88x92-drift region 204 may be selected so as to be as small as possible, taking into account the desired blocking capacity of the component. As a consequence thereof, it may be required that very thin wafers be processed, in the range of blocking capacities of 1 kV and less. This may be very expensive and may have only become possible in recent years. As an example of this, see T. Laska et al., Conf. Proc. ISPSD""97, pp. 361-364.
FIG. 8 shows a schematic cross-sectional representation of a PT-IGBT, whose active region, represented by reference numeral 100, has cell-shaped or strip-shaped MOS miniature-circuit-breaker assemblies 103, 106, 107, 108, 109. Specifically, in this context, reference numeral 108 designates a p-body zone, 106 an n+-source region, 107 a p+-contact region for connecting p-body zone 108 to a cathode terminal 101, which at the same time is connected to n+-source region 106, 103 a gate terminal, 109 a gate oxide, and 110 an intermediate oxide. Furthermore, 104 designates an nxe2x88x92-drift region and 150 an nxe2x88x92-buffer region, 105 a rear-side p+-emitter, and 102 an anode terminal.
The PT-IGBT according to FIG. 8 may be produced on a thick, p+-doped substrate, which simultaneously forms rear-side emitter region 105, having an epitactically-applied n-buffer region 150 and epitactically applied nxe2x88x92-drift region 104. Because, in order to achieve the smallest possible forward voltage drop, the thickness of nxe2x88x92-drift region 104 is selected so as to be smaller than is required by the width of the space-charge zone in the drift region at the desired blocking capacity, n-buffer region 150 may act to prevent a penetration of the space-charge zone to p+-emitter 105. In order to achieve a rapid switching off of the current despite good emitter 105, the charge-carrier service life may be kept short by a so-called lifetime killing, e.g., using electron irradiation, and/or the doping in n-buffer region 150 may be selected so as to be correspondingly heavy. Since the forward voltage may increase as the buffer dosage rises, it may be possible, using a heavily doped, thin buffer region 150, to achieve a good compromise between the forward voltage and the switch-off performance. A buffer of this kind may only be achieved to a limited degree using this type of double EPI/substrate wafer, due to the buffer diffusion in the manufacture of the raw wafer.
In what follows, a brief discussion of the mode of functioning of the aforementioned IGBT types is provided.
For the forward case, in both IGBT types, gate terminal 103, and 203, opposite cathode terminal 101, and 201, is set at a potential above the threshold voltage of MOS miniature-circuit-breaker assemblies 103, 106, 107, 108, 109, and 203, 206, 207, 208, 209. Subsequently, in the area of p-body region 108, and 208, an inversion channel may be produced on the semiconductor surface beneath gate terminal 103, and 203. The semiconductor surface in the area of nxe2x88x92-drift region 104, and 204, may then be in a condition of accumulation. In response to a positive voltage at anode terminal 102, and 202, opposite the cathode, electrons are injected into nxe2x88x92-drift region 104, and 204, through n+-source regions 106, and 206, the influenced MOS channels in body regions 108, and 208, and the accumulation layer.
Subsequently, anode-side emitter region 105, and 205, injects holes, as a result of which nxe2x88x92-drift region 104, and 204, is flooded by charge carriers such that its conductivity may be increased. In customary forward-current densities, the nxe2x88x92-drift region may be in a state of high injection. As a result, an IGBT having a blocking capacity beginning at roughly 150-200 volts may be capable of conveying higher current densities having a smaller voltage drop between anode and cathode than a MOS transistor having the same breakdown voltage. In the forward case, the current flows from the anode to the cathode. It is carried by electrons that are injected into nxe2x88x92-drift region 104, and 204, and that flow to the anode via anode-side emitter 105, and 205, and by holes which are injected by the anode-side emitter into nxe2x88x92-drift region 104, and 204, and which flow to the cathode via p-regions 107, 108, and 207, 208.
In the blocking case, gate terminal 103, and 203, opposite cathode terminal 101, and 201, is brought to a voltage below the threshold voltage. If anode terminal 102, and 202, is now brought to a positive potential, then the space-charge zone situated between p-body region 108, and 208, and nxe2x88x92-drift region 104, and 204, may expand virtually exclusively into nxe2x88x92-drift region 104, and 204.
In the case of NPT-IGBT, the thickness of nxe2x88x92-drift zone 204 may be selected so as to be greater than the width of the space-charge zone at a given maximum blocking capacity of the component. This may result in the triangular curve, indicated in FIG. 7, of electrical field intensity |E| along the y coordinate. The maximum field intensity may be located in region of the MOS miniature-circuit-breaker assemblies.
In the case of the PT-IGBT, the thickness of nxe2x88x92-drift zone 104 may be selected so as to be greater than the width of the space-charge zone would be at a given maximum blocking capacity of the component. To prevent the space-charge zone from running up against p+-emitter region 105, n-doped buffer zone 150 may be introduced so as to prevent the aforementioned punch-through. This may result in the trapezoidal curve, indicated in FIG. 8, of electrical field intensity |E| along the y coordinate. The maximum field intensity, here too, may be situated in the area of the MOS miniature-circuit-breaker assemblies.
FIG. 9 shows a conventional circuit topology, in which a vertical IGBT is used as ignition transistor 700 in the primary circuit of an ignition coil for an internal combustion engine. For this application as an ignition transistor, a V-IGBT may be used having a required blocking capacity of roughly 400-600 volts.
According to FIG. 9, the V-IGBT, having main terminals 701, 702 and gate terminal 703, is connected to battery voltage 711 via an ignition coil 712. On the secondary side of ignition coil 712, a spark plug 713 is provided. A diode 704, which is connected to gate terminal 708 via a resistor 707, may function as the ESD protection, and resistors 707, 714 (for example, having R707=1 kxcexa9 and R714=10-25 Kxcexa9), on the one hand, may establish the input resistance of the system and, on the other hand, may constitute the load of a clamp diode chain 705, 706. Components 704, 705, 706, 707, 714 may be integrated in a monolithic manner, diode 704, 705, 706 may be made of polysilicon.
The circuit arrangement in accordance with FIG. 9 may be directly operated by a suitable control unit via gate terminal 708. For this purpose, a positive voltage of, for example, 5 volts may be applied at gate terminal 708, whereupon a current rise may be injected through ignition coil 712. At a preestablished time point, the voltage at gate terminal 708 may be reduced step-by-step to roughly 0 volts, whereupon the voltage at node 709 may sharply increase. This voltage rise may be transformed upward to the secondary side of ignition coil 712 and may result in an ignition spark at spark plug 713.
Clamp diode chain 705, 706 may limit the voltage rise at anode terminal 702 to the so-called clamp voltage of roughly 400 volts, in order to protect, the IGBT and the further circuit components. This may be important in the so-called pulse case, which may arise when no ignition spark is generated, for example, as a result of a disconnected ignition cable. Then IGBT 700 may need to absorb the energy that may otherwise be converted in the spark. Without a voltage limitation of this type, the anode voltage at node 709, in this context, may increase to the point of the breakdown of IGBT 700 and may destroy the latter. This may be prevented by clamp diode chain 705, 706, as a result of the feature that, when a preselected clamp voltage is achieved, the chain may drive the gate of IGBT 700 just strongly enough so that the clamp voltage at node 709 is not exceeded. Nevertheless, as a result of the large amount of converted energy, this operational case may place high demands on the pulse resistance of the IGBT 700, which may not always be assured to the degree required. A negative consequence may be the destruction of IGBT 700.
J. Yedinak et al, Conf. Proc. ISPSD""1998, pp. 399-402 discusses that a failure may come about in the following manner.
In the pulse case, the space-charge zone may have engaged entire nxe2x88x92-drift region 104. As a result of a driving of the gate that is controlled using aforementioned clamp diode 705, 706, electrons, which drive p+-emitter 105, are injected into nxe2x88x92-drift region 104 through MOS channel configured in p-body region 108. As a result of the high current density, the high field intensity, and therefore the high power loss that may arise, the component may become very hot especially at the MOS miniature-circuit-breaker assemblies, whereupon an electrode leakage current may result. The electrons run in the direction of the anode, and there they may drive p+-emitter region 105 high. Thus they may bring about an additional driving of the IGBT. To maintain the voltage at the value of the clamp voltage, the driving of gate 103 may be reduced accordingly via the clamp diode chain. Under certain operating conditions, the driving as a result of the thermally caused electron leakage current may be so strong that the IGBT may conduct the load current without the gate being disconnected. Its controllability may be lost. The temperature may increase further, and the leakage current also may increase further. Finally, a thermal positive feedback may result, and the IGBT may be destroyed.
In addition to planar V-IGBT structures, discussed here, there may also be V-IGVTs having a so-called trench gate, in which the gate is introduced into the semiconductor surface in the form of a trench (I. Omura et al., Conference Proceedings ISPSD""97, pp 217-220). The mode of functioning of these trench-gate V-IGBTs may be entirely analogous to the structures discussed here; however, they may offer the advantage of a smaller forward voltage drop.
In German Published Patent Application No. 198 16 448, a universal semiconductor disk is described for high-voltage components and, inter alia, also for V-IGBTs, in which on an, e.g., nxe2x88x92-doped semiconductor substrate, at least one n-doped epitactical layer may be provided, which may be characterized by the feature that in the boundary surfaces between the substrate and the at least one epitactical layer a multiplicity of floating, p-doped semiconductor regions may be embedded, which may be dimensioned so that the dimension size of a floating region is small in comparison to the layer thickness of the at least one epitactical layer, and it essentially corresponds to the distance between the floating regions in a boundary surface, the distance being smaller than the dimension size. In this context, the floating regions lying in one plane may be connected to each other so that they constitute a grid. In the example of the V-IGBT, the assumption may be made that, in the active region of the V-IGBT, when a blocking voltage is applied, the charge carriers are not completely removed from the floating p-regions.
In German Published Patent Application No. 198 40 032, a MOS transistor (e.g., n-channel V-DMOS) having a non-floating compensation structure in the n-drift region is described. The latter may be characterized by the feature that the compensation structure and/or the n-drift region may be doped such that the degree of compensation changes toward the depths of the component in a monotonic fashion (continuously or step-by-step) as follows: in traversing the compensation structure from source to drain, on the source side, the p-doping dose may predominate over the n-doping dose, whereas on the drain-side end of the compensation structure, the n-doping dose may predominate over the p-doping dose. In response to a blocking voltage, a hump-shaped field distribution may be generated, which has its maximum roughly in the center of the vertical extension of the compensation structure, where n- and p-doping doses compensate for each other. Between the drain-side end of the compensation structure and the n+-substrate, a low-doped n-layer may be optionally arranged. The goal, in any case, may be increased processing reliability and increased robustness in breakdown.
German Published Patent Application No. 196 04 043, discusses favorably influencing the field distribution in a MOS transistor or V-IGBT, using the n-doped and p-doped regions that are permitted into the drift region, in order to reduce the forward voltage drop at a given blocking capacity. In this context, the total quantity of the doping of the introduced n-regions may be roughly the same as the total quantity of the doping of the introduced p-regions. In this context, the introduced regions may be distributed statistically or may be structured in spherical, strip, or filament shapes and may be introduced in pairs. Their separation may be greater than or equal to zero, but smaller than the space-charge zone. The p-regions may be executed so as to be floating. In the event of statistically distributed p- and n-regions, the average concentration of the distributed p-regions may be as great as or greater than the introduced n-regions. For manufacture, inter alia, a method is described which, beginning with a raw wafer, generates the p- and n-doped regions in the n-drift region using a multiple sequence of epitaxy, implantation, and diffusion.
A general problem underlying the present invention therefore may be seen in presenting a robust IGBT especially for ignition applications, which may have good conductive properties and a high pulse resistance, and which may be processed simply.
A semiconductor power component according to the present invention may provide a more robust IGBT having great pulse resistance without the requirement of processing thin wafers.
The semiconductor power component according to the present invention, in contrast to the structures proposed in German Published Patent Application No. 196 04 043, may be simpler to manufacture and, in contrast to the structures proposed in German Published Patent Application No. 198 40 032, may have increased pulse resistance. In particular, the semiconductor power components according to the present invention may permit small half-cell widths in a simple manner.
An idea underlying the present invention is that p-doped drift regions that are introduced into the n-drift region may be provided in strip and column shape, which may be connected to the cathode metal, e.g., via a p-body region having p+-contact diffusion, so that their potential may not float.
In contrast to conventional structures described in German Published Patent Application No. 196 04 043, in which two different (n- and p-) doped zone types are introduced, the structures according to the present invention may be manufactured more simply because only one additional type of drift region is introduced into the n-drift region.
Furthermore, the structures proposed here may be distinguished from those in German Published Patent Application No. 196 04 043 in that the total net dose of the p-regions introduced in the active region of the V-IGBT, e.g., per half-cell, is greater than the net dose of the part of the n-drift region that may be arranged in the active region between the p-drift regions.
The structures according to the present invention may be distinguished from those in German Published Patent Application No. 198 40 032, in that the degree of compensation K(y) may not decrease in a monotonic fashion from the first semiconductor surface y=0, having a y that grows toward the depths of the component. Rather, the degree of compensation may be set such that it has a maximum in the region of the end of the p-drift regions away from the first semiconductor surface.
According to one example refinement, between the first drift region and the rear-side emitter region, a buffer region of the second conductivity type may be provided.
According to a further example refinement, a contact region of the first conductivity type may partially surround the source region.
According to a further example refinement, the control contact may be a trench gate.
According to a further example refinement, the body region and the source region, on the one hand, and the third drift region, on the other hand, may run in a strip-shaped fashion and not parallel to each other. In contrast to the structures for vertical components described in German Published Patent Application No. 198 40 032, the MOS miniature-circuit-breaker assemblies to be laid out in strip-shaped fashion may be arranged so as to be not parallel to strip-shaped p-drift regions. Rather, the two may be mounted at roughly right angles to each other. This may bring with it advantages in the manufacturing process, as will be further discussed below.
According to a further example refinement, the third drift region may surround a trench filled with an insulating material.
According to a further example refinement, the first conductivity type maybe the p-type, and the second conductivity type may be the n-type.